1. Field of the Invention
This invention relates to an active matrix board for use in combination with a display medium, such as a liquid crystal display, for construction of a display apparatus.
2. Description of the Prior Art
An active matrix driving technique in which pixel electrodes arranged in a matrix fashion on an insulating substrate are independently driven has been employed in display apparatuses using liquid crystals. More especially, the active matrix driving technique has often been used in large-size display apparatuses having a high-density display function.
For use as a switching element for selectively driving the pixel electrodes there are generally known TFT (thin film transistor) elements, MIM (metal-insulating layer-metal) elements, MOS transistor elements, diodes, varistors, and the like. The active matrix driving technique permits high-contrast display and has already been actually incorporated in liquid-crystal TV sets, word processors, computer terminal display units, etc.
A circuit diagram for an active matrix display apparatus in which a TFT is used as a switching element is schematically shown in FIG. 9. A TFT 22 is disposed in the vicinity of each point of intersection between a plurality of parallel gate bus lines 23 acting as scan lines and a plurality of source bus lines 11 intersecting the lines 23 which act as signal lines. A pixel electrode is connected to the TFT 22, and between the pixel electrode and a counter electrode there is formed a picture element 21. An addition capacity 24 is formed between the pixel electrode and an addition capacity electrode.
FIG. 10 is a plan view showing a conventional active matrix board and FIGS. 11 and 12 are sectional views showing an active matrix display apparatus taken along lines A--A and B--B in FIG. 10, respectively. Parallel gate bus lines 23 are formed on a glass substrate 1 and, in intersecting relation with the lines 23, there are formed source bus lines 11. A gate insulation film 5 (FIG. 11) which will be described hereinafter is sandwiched between each gate bus line 23 and each source bus line 11.
A TFT 22 as a switching element is disposed adjacent each point of intersection between each gate bus line 23 and a source bus line 11. A gate electrode 26 of the TFT 22 is connected to the gate bus line 23, and a source electrode 27 of the TFT 22 is connected to the source bus line 11. A drain electrode 28 of the TFT 22 is connected to a pixel electrode 9.
An addition capacity line 31 is arranged in parallel to the gate bus line 23 and along a side of the pixel electrode 9 which is opposite to its side nearer to the gate bus line 23. An addition capacity electrode 32 is connected to the addition capacity line 31, the electrode 32 being opposed to the pixel electrode 9 so as to sandwich a gate insulation film 5 therebetween. An addition capacity 24 is formed between the addition capacity electrode 32 and the pixel electrode 9.
Sectional configurations of the gate bus line 23, addition capacity 24, and addition capacity line 31 will be explained with reference to FIG. 11. The gate bus line 23 consists of two layers, namely, a lower gate bus line 2 (2000 .ANG. thick) and an upper gate bus line 3 (2500 .ANG. thick). Likewise, the addition capacity line 31 consists of two layers, namely, a lower capacity bus line 29 (2000 .ANG. thick) and an upper capacity bus line 30 (2500 .ANG. thick). The lower gate bus line 2 and the lower capacity bus line 29 can be simultaneously pattern-formed. The lower gate bus line 2 and the lower capacity bus line 29 are both formed of a low-resistance metal, such as Mo, Al or the like.
For both the upper gate bus line 3 and the upper capacity bus line 30 Ta metal that can form an anodized film is used. Metals such as Mo, Al, and the like used for formation of the lower gate line 2 and lower capacity bus line 29 are less resistant to corrosion due to the action of fluoric acids or the like used as an etchant in a later process of the formation of TFT 22, and therefore the upper gate line 3 is so formed as to completely cover the lower gate line 2 for protection thereof. Likewise, the upper capacity bus line 30 is so formed as to completely cover the lower capacity bus line 29.
As above stated, both the gate bus line 23 and the addition capacity line 31 are composed of two layers and both the lower gate line 2 and the lower capacity bus line 29 are formed from such metals as Mo, Al or the like, whereby the specific resistance of the lines 23 and 31 can be lowered. Thus, it is possible to solve the problem of signal delay on the lines 23 and 31 which may arise in a larger-sized display apparatus. Moreover, the formation of an anodized layer on the upper surfaces of the lines 23 and 31 can reduce the possibility of a defective isolation occurrence with respect to the lines 23, 31.
The upper capacity bus line 30 is connected, at its portion parallel to one side of the pixel electrode 9, to the addition capacity electrode 32 located below the pixel electrode 9. The upper gate line 3, upper capacity bus line 30, and addition capacity electrode 32 are simultaneously pattern-formed. Therefore, the addition capacity electrode 32 is also formed from Ta.
On the upper gate line 3, upper capacity bus line 30, and addition capacity electrode 32, an anodized film 4 (3000 .ANG. thick) of Ta.sub.2 O.sub.5 is formed by anodizing their respective upper surfaces. A gate insulating film 5 (3000 .ANG. thick) of SiN.sub.x (silicon nitride) is formed on the entire surface of the substrate to cover the anodized film 4. A pixel electrode 9 (1000 .ANG. thick) made of ITO is formed on the gate insulating film 5. An addition capacity 24 is formed between the pixel electrode 9 and the addition capacity electrode 32 that faces the pixel electrode 9 so as to sandwich the gate insulating film 5 therebetween. Further, a protective film 16 (3000 .ANG. thick) of SiN.sub.x and an orientation film 17 are laid so as to completely cover the substrate, resulting in an active matrix board.
On a glass base 12 placed counter to the substrate 1 are provided a color filter 14 and black stripes 15 and, in addition, formed all over thereon are counter electrodes 13 made of ITO and an orientation film 17, resulting in an active matrix display apparatus.
TFT 22 will be explained according to the process of fabrication, with reference to FIG. 12. Gate electrodes 26 of Ta metal are formed simultaneously with the above mentioned gate lines 3, upper capacity bus lines 30, and addition capacity electrodes 32. The gate electrodes 26 are anodized simultaneously with the lines 3, 30 and electrodes 32, an anodized film 4 being thus formed on the gate electrodes 26. A gate insulating film 5 is formed over the substrate 1 to completely cover the anodized film 4.
Next, an intrinsic semiconductor amorphous silicon (hereinafter referred to as "a-Si(i)") layer (1000 .ANG. thick) is deposited on each gate electrode 26 so as to sandwich a gate insulating film 5 therebetween, the a-Si(i) layer functioning as a semiconductor layer 6. Moreover, on the a-Si(i) layer is deposited an n-type semiconductor amorphous silicon (hereinafter referred to as "a-Si(n.sup.+)") layer (500 .ANG. thick) which functions as contact layers 7.
Then, patterning is carried out on the a-Si(i) layer and the a-Si(n.sup.+) layer simultaneously to form a semiconductor layer 6 and contact layers 7. At this point of time, there is a portion yet to be removed by etching between the two contact layers 7, and therefore the two contact layers 7 are still connected to each other by that portion.
A Ti metal layer (3000 .ANG. thick) is placed all over the substrate and then patterning is effected on the Ti metal layer to form source electrodes 27 and drain electrodes 28. Simultaneously, the a-Si(n.sup.+) layer between the contact layers 7 is removed by etching. Pixel electrodes 9 (1000 .ANG. thick) made of ITO are pattern-formed on the drain electrodes 28 and gate insulating film 5. Further, the aforesaid protective film 16 and orientation film 17 are formed on the entire surface of the substrate.
In the above exemplified process, TFT 22 is formed only after the upper gate lines 3 and upper capacity bus lines 30 of Ta metal, anodized film 4, and gate insulating film 5 are formed on the lower gate lines 2 and lower capacity bus lines 29 of Mo or Al. Despite the fact that in this way three layers of films are formed on the lower gate lines 2 and lower capacity bus lines 29, there may be cases in which lower gate lines 2 and lower capacity bus lines 29 are eroded and become flattened out during the process of TFT 22 fabrication. Such erosion arises from pinholes developed in upper gate lines 3 and upper capacity bus lines 30, anodized film 4, and gate insulating film 5. The Mo or Al metal of which the lower gate lines 2 and lower capacity bus lines 29 are formed is, as already stated, less resistant to the action of a fluoric acid used as an etchant in the process of TFT 22 formation, and therefore the metal is easily eroded if any such pinhole is present therein. Such erosion may occur over a long distance along the length of each gate bus line 23 and each addition capacity line 31. Such erosion leads to troubles, such as increased resistance, line breakdown, and peeling, with respect to the gate bus lines 23 and addition capacity lines 31. Moreover, such erosion also leads to line breakdown, peeling, etc., with respect to the source bus lines 11.